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Jiale Yan (严佳乐)

Email: yjl16@tsinghua.org.cn / yanjiale@lixiang.com

NPU Architecture Senior Engineer | Li Auto, Shanghai, China

I work at computer architecture, efficient deep learning, and hardware-friendly algorithms for LLMs.

A current focus is LLM acceleration along two axes: scale-up (stronger single-node compute, memory, and dataflow) and scale-out (parallel training/inference across many accelerators with efficient communication).

  • Hardware acceleration: LLM/NPU accelerators, dataflow and memory-system co-design, GNN/SpMM accelerators.
  • Efficient ML: low-bit and sparse networks, memory-efficient transformers and large-model serving.
  • Broader interests: VLSI design, ray-tracing hardware, reconfigurable computing.

Hot! 🔥🔥🔥 I am always looking for self-motivated interns tailored to these topics. Feel free to reach out!

 Jiale Yan

LinkedIn  /  dblp

生而知之者，上也；学而知之者，次也；困而学之，又其次也；困而不学，民斯为下矣。　——孔子
Recent News
  • [2026] One paper accepted at ISCA 2026 (co-authored — thanks to my co-authors!).
  • [2026] Two papers accepted at CVPR 2026 (co-authored — thanks to my co-authors!).
  • [2025] Serving as Publicity Co-Chair for IEEE MCSoC 2026. Submissions welcome — see the conference website.
  • [2025/07] Science Tokyo news on BingoGCN: Real-time, large-scale graph neural network inference through BingoGCN.
  • [2025/06] BingoGCN covered by Nikkei (日本経済新聞).
  • [2025/04] Joined Li Auto as NPU Architecture Senior Engineer.
  • [2025] BingoGCN (first author) accepted at ISCA 2025.
Education

  • Sep. 2021 – Dec. 2024: Institute of Science Tokyo (formerly Tokyo Institute of Technology) (Ph.D.)

    Dissertation: Algorithm-architecture Collaborative Research toward Beyond-CNNs
    Ph.D. in Information and Communications Engineering
    Supervisor: Prof. Masato Motomura, IEEE Fellow, and Prof. Daichi Fujiki, Artic Lab, Institute of Science Tokyo

  • Sep. 2016 – Jul. 2019: Tsinghua University (THU) (Master)

    Dissertation: Research on Key Technologies of Energy Efficient and Reconfigurable Accelerator for Generative Neural Networks
    Master in Integrated Circuit Engineering
    Supervisors: Prof. Shaojun Wei, IEEE Fellow and Prof. Shouyi Yin, IEEE Fellow, Institute of Microelectronics

  • Sep. 2012 – Jun. 2016: Harbin Institute of Technology (HIT) (Bachelor)

    B.S. in Electronic Science and Technology

Professional Experience

  • Apr. 2025 – Present: Li Auto Company, Shanghai, China

    NPU Architecture Senior Engineer

  • Dec. 2024 – Apr. 2025: Science Tokyo, Researche, Tokyo, Japan

    AI Computing Researcher

  • Aug. 2019 – Aug. 2021: HiSilicon, Senior IC Engineer, Shanghai, China

    Ray-tracing Graphic Engine Designer

Academic Service
  • IEEE Data Competition Sub-Committee Member.
  • 2026 IEEE MCSoC Publicity Co-Chairs
  • Reviewer: IEEE TCSVT, Chinese Journal of Electronics, Learning on Graph Conference, IJCNN.


© 2026 Jiale Yan. Last updated May 2026.